Position Description
Responsibilities:
- Write verification design document
- Write code for automatic analysis
Qualifications:
- C++ experience
- Verilog or VHDL experience
- ASIC/FPGA development process experience
Preferred qualifications:
- Experience with system Verilog
- Experience in IP Networking L2/L3/L4
- Excellent human interface skills
- Thinking out of the box
To apply for this job, please send your CV to jobs@ethernitynet.com, or complete an online application below.
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