Data Plane Acceleration: More Recognition for FPGA

by Barak Perlman

Analysys Mason analysts Gorkem Yigit and Caroline Chappell have produced an excellent new technology overview white paper, titled Data plane acceleration technologies: realising the potential of network virtualization, in which they show how the transformation to software-defined, automated networks and the new era of cloud-based services for 5G and edge computing can only occur with data plane acceleration technologies, among them FPGA-based SmartNICs.

Here is their conclusion: “Acceleration technologies will be pivotal to this transformation by enabling operators to meet the performance, latency, QoS, subscriber density and security requirements of existing and future applications with optimum total cost of ownership.”

This is perfectly in line with our thinking here at Ethernity Networks. The white paper does a superb job of comparing the choices operators will need to make regarding the most appropriate data plane acceleration and offloading technologies for their application and workload needs, their networks, and their operational capabilities.

For example, the paper demonstrates a number of NFVI acceleration technologies, but proceeds to point out that it is possible to enhance software-centric options with hardware acceleration. “Operators are increasingly adopting accelerated vSwitch in their NFV/SDN deployments in conjunction with hardware-centric accelerators (for example, SmartNIC) to further enhance NFVI virtual networking performance and achieve a more-complete offload/acceleration of the OVS data path.”

What is required is careful evaluation of the cost, performance, programmability, and flexibility of the hardware-centric acceleration solutions, specifically FPGAs, multicore ASICs, and NPUs. Analysys Mason compares these options side-by-side, and a reading of their comparisons leads you to the same conclusions that we believe most operators will come to: FPGAs are the wise choice thanks to their programmability.

Multicore accelerators will be the best option under certain circumstances. As the white paper explains, “…fixed-function (ASIC) accelerators are preferable in scenarios where acceleration requirements are constant and maximum price-performance is desired (for example, 24/7 active security workloads).” However, multicore solutions come with hidden costs and significant extra time in the development process, which reduces the business justification for them considerably.

The paper rightly points out in the side-by-side comparison that the strongest argument against ASICs is their inflexibility. They can do what they were designed to do, but their functions can’t be reprogrammed once they are in place.

FPGAs get the highest marks for programmability, lifting them above NPUs as an acceleration option, but the white paper points out what the analysts consider shortcomings of FPGAs: costs and the fact that programming requires specialized skills or vendor support.

We would argue here that the rapid decreases in costs for FPGAs will continue and will negate the high-cost issue as their production ramps up due to the use of this technology in an ever-broadening range of industries, such as Gaming, Automotive, Consumer Electronics, Military, Aerospace, Healthcare, Cryptocurrency, and of course Telecommunications. In addition, for FPGA-based data plane acceleration systems from Ethernity Networks, because we are able to fit our networking and security firmware into smaller FPGAs, we can provide less costly units that reduce the final price of the solution. This also saves power and physical space, which is essential at the edge of the network where such factors are scarce, and application requirements are dynamic and require programmability. As the paper says, “FPGA would be ideal for edge deployments…”

We concede that programming is not a simple undertaking with FPGAs; however, the huge benefits of programmability outweigh the costs involved in the initial development and subsequent reprogramming of other acceleration options. It is also worth noting that almost every company except the giants will need to turn to expert vendors for programming, so this won’t be a competitive issue. To that end, Microsoft Azure concluded in its own white paper detailing its experiences with FPGA-based SmartNICs, “Designing your own FPGA might not be the natural choice for anyone beyond a large-scale cloud vendor.”

An additional downside to both NPUs and multicore accelerator technologies is that they have shown poor performance results when scaled above 40G. Given that the demand for 100G and beyond is imminent, FPGAs are a better option for futureproofing a network.

The bottom line: NFV and SDN networks need to offload key computing-intensive workloads from general-purpose CPUs to additional hardware and software acceleration components in order to reduce the cost per bit, and programmable, scalable FPGAs are a terrific option for providing that acceleration. We agree completely.