FPGAs for Disaggregating the 5G Network (with an excellent example)

5G infrastructure is a green field, with virtually no carry-over from legacy equipment.  As such, operators can now consider how to meet the insatiable demand for high bandwidth and low latency for 5G with an eye to the future and with less concern about the expense involved.

The solutions currently dominating the marketplace fall short of delivering in a number of ways. While the operator can select a software stack that supports all the required networking features, the underlying ASIC-based switch silicon could be a limiting factor. While most switches have a decent forwarding scale, many advanced features may be lacking. Problems arise if new functionalities cannot be added easily, if not all new tunneling protocols are supported, or if new security algorithms and holes cannot be easily accounted for.

Thus, it makes sense to ask:  why are we still using ASIC-based hardware for switching/routing at the edge?

Perhaps the current answer is that there is a lower capital expense incurred by using ASICs. That would account for the perplexing decision by multiple UK operators to replace Huawei equipment with similar ASIC-based equipment from Ericsson or Nokia. But considering that there are issues with rigid functionality and vendor lock-in with any ASIC-based solution, why are operators not using this golden opportunity to disaggregate and bring out the full potential of 5G?

In fact, at the edge it is even more important to achieve maximum flexibility in both the control and data planes, and given the evolving nature of the requirements in edge applications, futureproofing is exceptionally valuable. The long-term savings in operating expenses by fully disaggregating the hardware will far outstrip the added capital expense involved in migrating away from ASICs.

FPGAs offer complete network hardware disaggregation. An operator can select the required FPGA just as they would select the required CPU and processing power in a server. FPGAs are available from multiple vendors, all of which offer toolkits to enable development. Operators also have the freedom to choose the code that runs on an FPGA-based network interface card, selecting from an array of firmware vendors. It is also easy to port IP from one FPGA to another.

While FPGAs currently cost slightly more up-front in capital expenditure than ASIC-based devices (at least until 7nm FPGAs become the standard), they provide a huge advantage in that they add agility and futureproofing to the network edge. This is crucially important, at the very least until the 5G standards and benchmarks are finalized, and probably well beyond that.

FPGAs are an ideal platform for truly disaggregating hardware at the network edge, continuing the trend that was begun with NFV. It extends the concept to apply to white box edge switches and routers, as well as to optical line terminals (OLTs). FPGAs perfectly address the problems associated with the use of proprietary ASIC-based hardware platforms:  avoiding vendor lock-in and futureproofing the network, thereby saving on long-term operating expenses and reducing total cost of ownership.

In the excellent video from ServeTheHome at the bottom of this page, the Supermicro SYS-1019P-FHN2T edge server for 5G Distributed Unit is reviewed. The server comes with an Intel PAC N3000 FPGA-based card, which has the option of being bundled with 3rd-party IP. This is truly an example of how FPGA SmartNICs can serve as a programmable platform for disaggregation and acceleration of the open 5G network. The edge compute distribution platform is presented as part of the Open RAN concept, as opposed to Ericsson, Huawei, and Nokia’s closed platforms.

Ethernity can provide its own FPGA SmartNIC (the ACE-NIC100), which is the only card of its type with full routing functionality on FPGA, as well as clock synchronization, eCPRI aggregation, and the option for 5G FEC. Or Ethernity can partner with customers to customize the telecom features that are bundled onto 3rd-party hardware.

By Brian Klaff